Transistor with asymmetric source/drain overlap

ABSTRACT

An asymmetric field-effect transistor having different gate-to-source and gate-to-drain overlaps allows lower parasitic capacitance on the drain side of the device and lower resistance on the source side. Source and drain regions having different configurations can be formed simultaneously using the same precursor materials.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a division of U.S. patent application Ser. No.16/016,454 filed Jun. 22, 2018, the complete disclosure of which isexpressly incorporated herein by reference in its entirety for allpurposes.

BACKGROUND

The present invention relates generally to the electronic arts and, moreparticularly, to field-effect transistors and their fabrication.

There is a trade-off between source/drain series resistance and gate tosource/drain capacitance in the design of metal oxide semiconductorfield-effect transistors (MOSFETs). Specifically, FET saturated currentsare more sensitive to source resistance and less sensitive to drainresistance. FET drive current improves more with reduced sourceresistance than with reduced drain resistance. Additionally, circuitdelay is more sensitive to gate to drain capacitance than gate to sourcecapacitance. That is, due to the Miller effect, the gate to draincapacitance can impact circuit delay significantly more than gate tosource capacitance. However, some techniques associated with reducingsource/drain resistance to improve drive current often simultaneouslyincrease the gate to drain capacitance, thereby increasing circuitdelay. Similarly, some techniques associated with reducing gate tosource/drain capacitance often simultaneously increase sourceresistance, thereby degrading drive current. Thus, there is often anintrinsic trade-off between decreasing source resistance to improvedrive current and decreasing gate to drain capacitance to minimizecircuit delay.

BRIEF SUMMARY

Asymmetric field-effect transistor structures and techniques forfabricating such structures are disclosed.

In one aspect, an exemplary asymmetric field-effect transistor deviceincludes a semiconductor substrate including a first region, a secondregion, and a channel region between the first and second regions. Thefirst region including a recess extending vertically therein. The secondregion does not include a recess. A gate electrode including a drainside and a source side is operatively associated with the channelregion. A gate dielectric layer is between the gate electrode and thechannel region. A doped epitaxial source region is on the first regionof the semiconductor substrate and extends within the recess. A dopedepitaxial drain region is on the second region of the semiconductorsubstrate.

In another aspect, an exemplary method includes obtaining a structureincluding a semiconductor substrate having a first portion including arecess extending vertically therein, a second portion lacking a recess,and a channel region between the first and second portions. An embeddedsource region is epitaxially grown within the recess in the firstportion of the semiconductor substrate and a cladded drain region isepitaxially grown on the second portion of the semiconductor substrate.A gate dielectric layer is deposited over the channel region of thesemiconductor substrate and a metal gate is formed on the gatedielectric layer.

A further method of fabricating an asymmetric field-effect transistordevice includes obtaining a structure including a semiconductorsubstrate, sacrificial mandrels on the semiconductor substrate, dummygates on sidewalls of the sacrificial mandrels, and a vertical trenchbetween a pair of the dummy gates. The vertical trench is filled with afilling material having a different composition from the mandrels anddummy gates. The mandrels are selectively removed to expose firstportions of the semiconductor substrate. The first portions of thesemiconductor substrate are subjected to a first etching process,thereby forming first recesses within the first portions of thesemiconductor substrate. The filling material is removed from thevertical trench to expose a second portion of the semiconductorsubstrate. The first and second portions of the semiconductor substrateare subjected to a second etching process, thereby enlarging the firstrecesses within the first portions of the semiconductor substrate andforming a second recess in the second portion of the semiconductorsubstrate, the first recesses extending further vertically within thesemiconductor substrate than the second recess following the secondetching process. Embedded source and drain regions are epitaxially grownwithin the first and second recesses in the semiconductor substrate. Thedummy gates are removed and replaced with a gate dielectric layer andmetal gate material on the gate dielectric layer.

Techniques and devices as disclosed herein can provide substantialbeneficial technical effects. By way of example only and withoutlimitation, one or more embodiments may provide one or more of thefollowing advantages:

-   -   Precise overlay of source/drain patterning mask over a small        gate not required;    -   Self-aligned sidewall image transfer (SIT) process enables        asymmetry;    -   Greater gate-to-source junction overlap and smaller        gate-to-drain junction overlap;    -   Different source/drain epitaxial configurations can be grown        simultaneously;    -   Different fin pitches not required for fabrication of asymmetric        transistors;    -   Lower resistance on the source side and lower parasitic        capacitance on the drain side.

These and other features and advantages will become apparent from thefollowing detailed description of illustrative embodiments thereof,which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The following drawings are presented by way of example only and withoutlimitation, wherein like reference numerals (when used) indicatecorresponding elements throughout the several views, and wherein:

FIG. 1 is a schematic, cross-sectional view depicting a finnedsemiconductor substrate having mandrels formed thereon;

FIG. 2 is a cross-sectional view showing the structure of FIG. 1following formation of dummy gate spacers on the mandrels;

FIG. 3 is a schematic, cross-sectional view showing the structure ofFIG. 2 following deposition of fill material between the spacers;

FIG. 4 is a schematic, cross-sectional view thereof following removal ofthe mandrels from the structure shown in FIG. 3;

FIG. 5 is a schematic, cross-sectional view of the structure of FIG. 4following etching of the finned substrate to form lateral undercuts inthe source regions of the substrate;

FIG. 6A is a schematic, cross-sectional view thereof following removalof the fill material between dummy gate spacers;

FIG. 6B is a schematic, cross-sectional view of an alternativeembodiment following formation of recesses in the substrate on both thesource and drain sides of the dummy gate spacers;

FIG. 7A is a schematic, cross-sectional view of the structure shown inFIG. 6A following formation of source/drain regions between dummy gates;

FIG. 7B is a schematic, cross-sectional view showing formation of sourceand drain regions during the fabrication of a planar, asymmetricfield-effect transistor;

FIG. 8 is a schematic, cross-sectional view of the structure shown inFIG. 8 following deposition of an interlevel dielectric (ILD) layer andplanarization;

FIG. 9 is a schematic, cross-sectional view following removal of thedummy gates and formation of replacement metal gates in the structureshown in FIG. 8;

FIG. 10 is a top plan view of an asymmetric FinFET with embedded sourceepitaxy and cladding drain epitaxy;

FIG. 10A is a schematic, cross-sectional view thereof taken along theplane of line A-A in FIG. 10;

FIG. 10B is a schematic, cross-sectional view thereof taken along theplane of line S-S in FIG. 10; and

FIG. 10C is a schematic, cross-sectional view thereof taken along theplane of line D-D in FIG. 10.

It is to be appreciated that elements in the figures are illustrated forsimplicity and clarity. Common but well-understood elements that may beuseful or necessary in a commercially feasible embodiment may not beshown in order to facilitate a less hindered view of the illustratedembodiments.

DETAILED DESCRIPTION

Principles of the present invention will be described herein in thecontext of an illustrative asymmetric field-effect transistor fabricatedon a silicon substrate. It is to be appreciated, however, that thespecific embodiments and/or methods illustratively shown and describedherein are to be considered exemplary as opposed to limiting. Moreover,it will become apparent to those skilled in the art given the teachingsherein that numerous modifications can be made to the embodiments shownthat are within the scope of the claims. That is, no limitations withrespect to the embodiments shown and described herein are intended orshould be inferred.

The figures schematically illustrate an exemplary sequence offabrication steps that may be employed in obtaining an asymmetricfield-effect transistor. Although the overall fabrication method and thestructures formed thereby are novel, certain individual processing stepsrequired to implement the method may utilize conventional semiconductorfabrication techniques and conventional semiconductor fabricationtooling. These techniques and tooling will already be familiar to onehaving ordinary skill in the relevant arts given the teachings herein.While some individual processing steps are set forth herein, those stepsare merely illustrative, and one skilled in the art may be familiar withseveral equally suitable alternatives that would be applicable.

With reference now to the structure 30 shown in FIG. 1, a bulk siliconwafer 32 is employed as the substrate in some embodiments. The substrateconsists essentially of mono-crystalline silicon in one or moreembodiments. Single crystal silicon wafers are commercially availableand are characterized by a diamond cube lattice structure. As known inthe art, the Miller indices of a substrate are determined from thereciprocals of the points at which the crystal plane of siliconintersects the principle crystalline axes. While some exemplaryembodiments relate to structures including doped or undoped (100)silicon as a substrate material, it will be appreciated that theprinciples expressed are applicable to other semiconductor substratesand substrates with crystallographic orientations other than (100). Forexample, substrates such as semiconductor-on-insulator (SOI) substratesas well as bulk substrates can be employed in accordance with theteachings herein.

Referring again to FIG. 1, a pad layer 34 such as a pad oxide or padnitride layer is formed on the substrate. As known in the art, a thinsilicon oxide or silicon nitride layer can be grown on a silicon waferas a protective layer to facilitate downstream processes. Electricallyisolated active regions are then formed from the substrate by techniquessuch as shallow trench isolation (STI). Each active region can compriseplanar semiconductor structures, fin structures, nanowires, nanosheets,or any other suitable semiconductor materials.

Vertical mandrels 36 are formed on the substrate. The sacrificialmandrels may comprise, for example, amorphous silicon (a-Si) orpolycrystalline silicon (polysilicon). The sacrificial materialcomprising the mandrels may be deposited by a deposition process suchas, but not limited to, physical vapor deposition (PVD), chemical vapordeposition (CVD), plasma enhanced chemical vapor deposition (PECVD),inductively coupled plasma chemical vapor deposition (ICP CVD), atomiclayer deposition (ALD), or any combination thereof. Hydrogenatedamorphous silicon is typically deposited by plasma-enhanced chemicalvapor deposition (PECVD) although other techniques such as hot-wirechemical vapor deposition (HWCVD) may be used. A layer of suchsacrificial material is patterned to obtain discrete mandrels havingsubstantially vertical side walls. A patterned mask (not shown)including openings corresponding to the mandrel locations may be formedon the layer of sacrificial material. The sacrificial material is thensubjected to a reactive ion etch to remove the sacrificial materialbetween the mandrels 36 down to the pad layer 34, which functions as anetch stop. The mandrels 36 may or may not have the same width. In someembodiments, mandrel width is in the range of ten to fifty nanometers(10-50 nm) and mandrel height is fifty to one hundred fifty nanometers(50-150 nm). Mandrel dimensions are exemplary and not limiting.

Referring to FIG. 2, spacers/dummy gates 38 are formed on the mandrelsidewalls. Silicon nitride spacers/dummy gates are formed in someembodiments. A silicon nitride layer can be deposited via CVD, PECVD,sputtering, or other suitable technique to form the spacers. Amorphouscarbon spacers/dummy gates are formed on the mandrel sidewalls in otherembodiments using chemical vapor deposition (CVD) or other suitableprocess. The material chosen for spacer/dummy gate formation should becompatible with subsequent processing steps as described below.Spacer/dummy gate thickness is between ten and fifty nanometers (10-50nm) in some embodiments. The spacers can be formed by any method knownin the art, including depositing a conformal layer over the substrateand mandrels 36 and removing unwanted material using an anisotropicetching process such as reactive ion etching or plasma etching. Theresulting structure includes trenches 40 between each set of mandrelsand adjoining spacers/dummy gates and extending down to the pad layer34. The trenches 40 may or may not have equal widths. Trench width canbe in the range of ten to fifty (10-50 nm) in the exemplary embodiments.

A filler material is deposited in the trenches 40 in obtaining astructure as schematically illustrated in FIG. 3. The filler materialadjoins the drain sides 38A of the dummy gates while the mandrels 36adjoin the source sides 38B thereof. The filler material is different incomposition from the materials comprising the mandrels 36 andspacers/dummy gates 38, which allows for selective etching thereof.Non-limiting examples of materials for the filler layers 42 includeamorphous carbon, silicon dioxide, tetraethylorthosilicate (TEOS) oxide,high aspect ratio plasma (HARP) oxide, high temperature oxide (HTO),high density plasma (HDP) oxide, oxides (e.g., silicon oxides) formed byan atomic layer deposition (ALD) process, or any combination thereof.The resulting structure is planarized, for example by chemicalmechanical planarization (CMP), to obtain the structure shown in FIG. 3.The heights of the mandrels 36, spacers/dummy gates 38 and filler layers42 comprising the structure are substantially the same. As discussedfurther below, the regions occupied by adjoining mandrels 36,spacers/dummy gates 38 and filler layers 42 can later be employed toform source, gate and drain regions of asymmetric field-effecttransistors. The spacers/dummy gates 38 may accordingly be employed asdummy gates that are replaced by metal gate material during subsequentprocessing. The dummy gates have source sides and drain sides.

The mandrels 36 are removed to form a structure as shown in FIG. 4. Inembodiments including amorphous silicon mandrels, a wet etch using hotammonia can be employed to selectively remove the mandrels while leavingthe spacers/dummy gates 38 and the oxide layers 42, 34 substantiallyintact. Trenches 44 are accordingly formed between selected pairs ofspacers/dummy gates 38.

The pad oxide layer is removed from the bottoms of the trenches 44using, for example, a wet etching process including a hydrofluoric (HF)acid mixture. The substrate 32 is then subjected to a wet etchingprocess to further extend the trenches 44 vertically and laterally inthe portions of the substrate to be employed for growing source regions.The lateral undercut is optional. In embodiments where lateralundercutting is deemed unnecessary, a vertical recess can be formed by adirectional etch such as reactive ion etch (RIE) process. If bothvertical and lateral etching are desired, either a single isotropicetch, or a combination of anisotropic etch and isotropic etch can beused. The adjoining dummy gates 38 and remaining portions of the padoxide layer function as an etch mask during etching of the substrate.Recesses 44′ within the semiconductor substrate can be formed using ananisotropic etching (e.g., reactive ion etch (RIE)), an isotropic etch(e.g., chemical downstream etch) or a combination of both isotropic andanisotropic etching. The recesses can be bowl shaped, sigma shaped, orother shape configuration as a result of the chosen recess process(es).A wet etch containing ammonia (NH₄OH) may, for example, be employed forthe isotropic etching of silicon. Alternatively, a RIE process can beused to vertically recess Si fins. Optionally, this process is timed sothat the substrate is laterally etched by about 3-10 nm beneath thedummy gates, so that the edges of the recesses 44′ after the pullbackare located under the dummy gates 38 and the portions of the pad oxidelayer 34 beneath the dummy gates. The depths of the recesses 44′ may bebetween twenty and sixty nanometers (20-60 nm).

The filler layers 42 between the drain sides 38A of the spacers/dummygates 38 are removed to form additional trenches 48 extending down tothe portions of the substrate 32 used for growing drain regions, asshown in FIG. 6A. A selective etch may be employed to remove the fillermaterial, leaving the spacers/dummy gates 38 substantially intact. Inone embodiment, the filler layer 42 comprises amorphous carbon that canbe selectively etched, for example, by ozone gas etching, or by oxygenplasma etching. Alternatively, amorphous carbon can be selectivelyetched by wet etch containing sulfuric acid and peroxide. If the fillerlayer 42 is oxide, it and the underlying portions of the pad oxide layer34 can, for example, be selectively etched using CHF₃/Ar plasma or a wetetch containing hydrofluoric acid.

Referring to FIG. 7A, source and drain regions 50A, 50B are formed onthe substrate. The drain regions are aligned with the trenches 48formerly containing the fill layers 42. The source regions are alignedwith the trenches 44 formerly containing the mandrels and fill thelaterally enlarged recesses 44′ within the substrate. Optionally, thesubstrate 32 is also recessed following removal of the fill layers 42 toform recesses 48′ in the substrate before drain epitaxy, as shown inFIG. 6B. Epitaxial structures are then grown inside both sets ofrecesses. In embodiments in which both source and drain substrate areasare recessed, after a first recess of the source areas such as shown inFIG. 5 or instead using only a directional etch, both the drain andsource areas will be recessed following removal of the fill layer 42over the drain area. This procedure resulting in greater etching of thesource sides than the drain sides of the dummy gates 38 because drainsides of the substrate have been recessed only once and source sideshave been recessed twice. As shown in FIG. 6B, the source side recesses44″ are deeper than the drain-side recess 48′. In the exemplaryembodiment shown in FIG. 7A, the drain side is not recessed; the drainside has cladding epitaxy 50B on fin sidewalls, and the source side hasembedded epitaxy 50A (epitaxy in the recessed region 44′). In otherwords, the drain epitaxy 50B is directly grown on the exposed surface ofthe semiconductor substrate in the drain region and there is norecessing of the substrate under the trenches 48. Epitaxial growthwithin substrate recesses, as conducted during the epitaxial growth ofthe source regions, may be characterized as “embedded epitaxy.”Epitaxial growth of drain regions on substrate fins that have not beenrecessed is characterized as “cladding epitaxy.” FIG. 7A shows theoptional case including recesses 44′ only in the source regions,resulting in embedded epitaxy on the source side 38B of each dummy gateand cladding epitaxy on the drain side 38A thereof.

The terms “epitaxially growing and/or depositing” and “epitaxially grownand/or deposited” mean the growth of a semiconductor material on adeposition surface of a semiconductor material in which thesemiconductor material being grown has the same crystallinecharacteristics as the semiconductor material of the deposition surface.In an epitaxial deposition process, the chemical reactants provided bythe source gases are controlled and the system parameters are set sothat the depositing atoms arrive at the deposition surface of thesemiconductor substrate with sufficient energy to move around on thesurface and orient themselves to the crystal arrangement of the atoms ofthe deposition surface. Therefore, an epitaxial semiconductor materialhas the same crystalline characteristics as the deposition surface onwhich it is formed. The dopants may be incorporated in situ usingappropriate precursors, as known in the art. By “in situ” it is meantthat the dopant that dictates the conductivity type of a doped layer isintroduced during the process step, e.g., epitaxial deposition thatforms the doped layer. As used herein, the term “conductivity type”denotes a dopant region being p-type or n-type. As used herein, “p-type”refers to the addition of impurities to an intrinsic semiconductor thatcreates deficiencies of valence electrons. In a silicon-containingsubstrate, examples of p-type dopants, i.e., impurities include but arenot limited to: boron, aluminum, gallium and indium. As used herein,“n-type” refers to the addition of impurities that contribute freeelectrons to an intrinsic semiconductor. In a silicon-containingsubstrate, examples of n-type dopants, i.e., impurities, include but arenot limited to antimony, arsenic and phosphorous. Exemplary epitaxialgrowth processes that are suitable for use in forming silicon and/orsilicon germanium epitaxy include rapid thermal chemical vapordeposition (RTCVD), low-energy plasma deposition (LEPD), ultra-highvacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemicalvapor deposition (APCVD) and molecular beam epitaxy (MBE). Such growthresults in faceted structures that, in some cases, merge into acontinuous volume and in other cases remain isolated. Source and draingrowth can be effected simultaneously and provide source and drainregions comprising the same epitaxial materials but having differentconfigurations. In some embodiments, a portion or all dopants can beincorporated in source/drain regions by other suitable doping technique,including but not limited to, ion implantation, gas phase doping, plasmadoping, plasma immersion, ion implantation, cluster doping, infusiondoping, liquid phase doping, solid phase doping, or any suitablecombination of those doping techniques.

Referring to FIG. 8, an interlevel dielectric (ILD) layer 54 isdeposited on the structure and fills the trenches 44, 48 above thedoped, epitaxial source and drain regions 50A, 50B. The ILD layer 54 maybe formed from any suitable dielectric material, including but notlimited to spin-on-glass, a flowable oxide, a high density plasma oxide,borophosphosilicate glass (BPSG), or any combination thereof. The ILDlayer is deposited by any suitable deposition process including but notlimited to CVD, PVD, plasma-enhanced CVD, atomic layer deposition (ALD),evaporation, chemical solution deposition, or like processes. In someembodiments, ILD layer 54 may comprise a single layer (e.g., oxide) ormultiple layers (e.g., a silicon nitride liner followed by oxide fill).The ILD layer is planarized using chemical mechanical planarization(CMP), as known in the art, to obtain a structure as schematicallyillustrated in FIG. 8. The top surfaces of the spacers/dummy gates 38are exposed following CMP.

The spacers/dummy gates 38 and the portions of the pad oxide layer 34beneath the dummy gates are removed from the structure shown in FIG. 8as part of a replacement metal gate (RMG) process. If the spacers/dummygates 38 are amorphous carbon, they can be removed by using oxygenplasma or ozone etch. If the spacers/dummy gates are silicon nitride,they can be removed either using a wet etch (e.g., aqueous solutioncontaining phosphoric acid) or dry etch (e.g., a plasma containingSF₆/CH₄/N₂/O₂ plasma). The sidewalls of the ILD layer 54 are alsooptionally trimmed to reduce the widths thereof following spacer/dummygate removal.

A set of dielectric sidewall spacers 46 is formed on the sidewalls ofthe columns of ILD material, as schematically illustrated in FIG. 9. Itwill be noted that the ILD columns have reduced widths in this exemplaryembodiment, having been trimmed using a reactive ion etch or othersuitable trimming process. The dielectric sidewall spacers 46 mayconsist essentially of, for example silicon oxide, silicon oxynitride,silicon nitride, SiBCN (siliconborocarbonitride) or SiOCN(siliconoxycarbonitride), SiOC (siliconoxycarbide). A conventionalspacer formation process, namely, a conformal deposition process (e.g.,ALD or CVD) followed by an anisotropic etch process (e.g., RIE) thatacts to remove the just-deposited material from the horizontal surfaces,may be employed to form the sidewall spacers 46. Sidewall spacerthickness is between one and three nanometers (4-8 nm) in someembodiments. The thickness of the sidewall spacers 46 on each sidewallof the ILD columns 54 is substantially the same in some embodiments. Thesidewall spacers 46 of the completed device will accordingly have thesame thickness on both the source side and the drain side of the gateelectrode in some embodiments.

A gate dielectric layer 56 forms portions of the gate stack that replacethe spacers/dummy gates 38 for the asymmetric transistor devices to befabricated. The gate dielectric layer 56 adjoins the sidewall spacers 46and the channel regions within the semiconductor substrate and betweenthe source and drain regions 50A, 50B. Non-limiting examples of suitablematerials for the gate dielectric layer 56 include oxides, nitrides,oxynitrides, silicates (e.g., metal silicates), aluminates, titanates,nitrides, or any combination thereof. Examples of high-k materials (witha dielectric constant greater than 7.0) include, but are not limited to,metal oxides such as hafnium oxide, hafnium silicon oxide, hafniumsilicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconiumoxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalumoxide, titanium oxide, barium strontium titanium oxide, barium titaniumoxide, strontium titanium oxide, yttrium oxide, aluminum oxide, leadscandium tantalum oxide, and lead zinc niobate. The high-k material mayfurther include dopants such as, for example, lanthanum and aluminum.The gate dielectric layer 56 may be formed by suitable depositionprocesses, for example, chemical vapor deposition (CVD), plasma-enhancedchemical vapor deposition (PECVD), atomic layer deposition (ALD),evaporation, physical vapor deposition (PVD), chemical solutiondeposition, or other like processes. The thickness of the gatedielectric material may vary depending on the deposition process as wellas the composition and number of high-k dielectric materials used. Insome embodiments, the gate dielectric layer includes multiple layers.

Electrically conductive gate material is deposited in the regionsformerly containing the spacers/dummy gates 38. The deposited metal gatematerial form the metal gates 58 of the asymmetric field-effecttransistors, as shown in FIG. 10. The metal gates 58 include a sourceside and a drain side. The metal gates 58 overlap portions of thelaterally enlarged source regions 50A in some embodiments. Non-limitingexamples of suitable electrically conductive metals for forming themetal gate include aluminum (Al), platinum (Pt), gold (Au), silver (Ag),tungsten (W), titanium (Ti), cobalt (Co), or any combination thereof.The gate metal may be deposited using processes such as CVD, PECVD, PVD,plating, thermal or e-beam evaporation, or sputtering. A planarizationprocess, for example, chemical mechanical planarization (CMP), isperformed to polish the top surface of the deposited gate metalmaterial. The asymmetry of the source and drain regions formed using theprocess described above results in less gate/junction overlap on thedrain side of the device and greater gate/junction overlap on the sourceside of the device.

Source/drain junctions can be formed by trimming the ILD columns 54 sothat portions of the source and drain regions will extend beneath thespacers and/or by dopant diffusion from the source/drain epitaxy(regions 50A, 50B) into the semiconductor substrate 32. Techniques suchas rapid thermal anneal (RTA), flash anneal, laser anneal, or anysuitable combination of those annealing techniques, may be employed tocause dopant diffusion and formation of source/drain junctions inembodiments wherein the ILD columns are not trimmed. The junctionsextend laterally from the source and drain regions. Thermal annealingcauses the diffusion of dopants from doped source/drain regions towardschannel to form gate-to-source/drain overlapping. The dopant diffusionanneal can be performed immediately after source/drain formation (FIG.7), or after high-k gate dielectric formation. In practice, a highthermal budget anneal after gate metal formation is typically avoided.In embodiments wherein the ILD columns are trimmed, both the source anddrain regions 50A and 50B have portions directly beneath the bottom endsof the sidewall spacers 46. If the ILD columns are not trimmed, only therelatively wide (laterally extended) source regions will have portionsdirectly beneath a pair of sidewall spacers 46 prior to dopantdiffusion.

In some embodiments, the electrically conductive gates can include awork function metal (WFM) layer (not shown) disposed between the gatedielectric layer and another electrically conductive metal gatematerial. The WFM sets the transistor characteristics such as thresholdvoltage (Vt) to a predetermined value. In some embodiments, the WFMserves dual purposes: Vt setting and gate conductor. Non-limitingexamples of suitable work function metals include p-type work functionmetal materials and n-type work function metal materials. P-type workfunction materials include compositions such as ruthenium, palladium,platinum, cobalt, nickel, and conductive metal oxides, titanium nitride,or any combination thereof. N-type metal materials include compositionssuch as hafnium, zirconium, titanium, tantalum, aluminum, metal carbides(e.g., hafnium carbide, zirconium carbide, titanium carbide, andaluminum carbide), aluminides, or any combination thereof. The workfunction metal(s) may be deposited by a suitable deposition process, forexample, ALD, CVD, PECVD, PVD, plating, thermal or e-beam evaporation,and sputtering.

The gate metal and adjoining gate dielectric/WFM layer are recessed toform cavities between the spacers 46. A timed directional reactive ionetch may be employed to perform etch-back of the gate metal. A mask (notshown) may be applied and patterned prior to etching portions of thestructure. The recesses above the gate metal are filled with adielectric material to form dielectric caps 60 that can protect themetal gates during self-aligned contact (SAC) etch, as shown in FIG.10A. The caps may be formed from materials such as silicon nitride tofacilitate a self-aligned contact (SAC) process, ensuring requisiteselectivity for the SAC etch. After deposition, the dielectric capmaterial is planarized to remove it from the surface of the structure.The dielectric cap material remains within the recesses above the gatemetal following planarization. Dielectric caps prevent shorting betweenthe metal gates and subsequently formed self-aligned contacts 62. Asknown in the art, self-aligned contacts facilitate alignment duringfabrication of integrated circuit devices having small dimensions. Suchcontacts have been formed by depositing metals such as aluminum andtungsten in trenches formed in dielectric materials while avoidingelectrical contact with metal gate material of the FinFETs. Self-alignedcontacts 60 are accordingly formed within a replacement metal gateprocess while preventing gate to contact shorts.

The source/drain contacts 60 are formed any suitable patterning andmetallization processes. For example, a mask can be used to open theareas where source/drain contacts are needed. The exposed ILD 54 isremoved to form contact trenches on top of the source/drain regions.Conductive material(s) can then be deposited in the trenches followed byplanarization to form source/drain contacts. The ILD material can beremoved by any suitable etch process. For example, it can be removed byRIE containing CHF₃/Ar plasma. ILD material above unused source or drainregions may remain on the structure. Contact material may, for example,include tantalum (Ta), aluminum (Al), platinum (Pt), gold (Au), tungsten(W), titanium (Ti), cobalt (Co) palladium (Pd) or any combinationthereof. The contact material may be deposited by, for example, CVD,PECVD, PVD, plating, thermal or e-beam evaporation, or sputtering. Thecontact material may include a liner on trench sidewalls before fillingthe rest of the trench with an electrically conductive metal.Non-limiting liner materials include titanium nitride (TiN), tantalumnitride (TaN). A planarization process such as CMP is performed toremove any conductive material from the top surface of the structure100. In some embodiments, insulator caps (not shown) can be formed ontop of the source/drain contacts. The formation of the insulator caps onsource/drain contacts is similar to the formation of the insulator capon gate (e.g., recessing source/drain contacts, depositing andplanarizing an insulator). The process described above allows greateroverlap of the junctions extending from the source regions 50A with thegate stack and therefore a greater contact area between the sourcejunctions and the gate stacks. Electrical resistance is relatively low.There is less overlap of the junctions on the drain sides with the metalgates. The relatively small contact area between the junctionsassociated with the drain regions and the bottom ends of the gate stacksresults in relatively low parasitic capacitance.

By taking advantage of the self-aligned sidewall image transfer processto enable asymmetry, as described above, the fabrication process doesnot require precise overlay of a source/drain patterning mask on a smallgate. The formation of an asymmetric field-effect transistor having asmall gate length can be challenging. Patterning one side of thetransistor and processing the other side can create overlay/misalignmentissues that are substantially avoided using the techniques describedherein.

FIGS. 10, 10A, 10B and 10C provide various views of an exemplarystructure 100. FIG. 10 is a schematical, top plan view of the structure100 showing the gate regions 58 extending across an array of parallelfins 32′ formed from the substrate 32. It will be appreciated that thefins 32′ may or may not have sidewalls that are entirely vertical. Thebottoms of the fins 32′ may in fact be larger in width than the topportions thereof. For example, if the substrate 32 in an exemplaryembodiment is a (100) substrate, the side wall surfaces of thesemiconductor fins described as (110) surfaces are at least close tobeing (110) surfaces but may or may not be exactly (110) surfaces. Finwidth dimensions are accordingly average dimensions where fin width isnot uniform.

Each asymmetric field-effect transistor device within the exemplarystructure includes a semiconductor substrate 32, a doped epitaxialsource region 50A on the semiconductor substrate 32, and a dopedepitaxial drain region 50B on the semiconductor substrate. Asschematically illustrated in FIG. 10B, the source region epitaxy, beingformed in recesses having laterally extending portions, comprisesembedded epitaxial structures that extend beneath the top surface of theSTI layer 64. The drain region epitaxy is formed on the fin sidewalls(cladding epitaxy) in the illustrated embodiment and over the top endsof the fins, but does not extend below the top surface of the STI layer.The bottom portions of the fins 32′ are embedded within the electricallyinsulating shallow trench isolation (STI) layer 64. The semiconductorchannels 50C beneath the gate regions 58 are operatively associated withthe doped epitaxial source region and the doped epitaxial drain region.Each gate electrode 58 includes a drain side and a source side. Thesource regions 50A extend beneath the source sides of the gateelectrodes 58 in some embodiments. The widths of the top portions of thesource regions 50A exceed the widths of the top portions of the drainregions 50B and therefore extend further towards the channel regions 50Cthan the drain regions 50B. A gate dielectric layer 56 is between eachgate electrode and the channel region operatively associated therewith.In some embodiments, by having embedded epitaxy as the source andcladding epitaxy as the drain, epitaxy volume in the source is greaterthan that in drain because drain side still have the original undopedfin. By using the same thermal anneal, there will be more junctionoverlap on the source side than the drain side because of more dopantatoms in source side than the drain side.

While the fabrication process and resulting devices have been describedwith respect to silicon-based transistors, it will be appreciated thatmaterials other than those described herein, such as III-V compoundsemiconductor materials, can be employed in the formation offield-effect transistors having asymmetric source/drain regions. Thetechniques and concepts disclosed herein can be applied in thefabrication of various types of field-effect transistors, includingplanar transistors. By employing techniques substantially as describedabove to obtain a planar transistor, the drain will comprise raisedepitaxy (epitaxy on top of the surface of the substrate on drain side),and the source will comprise embedded epitaxy. FIG. 7B schematicallyillustrates the formation of source and drain regions during thefabrication of a planar transistor. Such techniques and concepts arefurther applicable to non-planar transistors (e.g. FinFET, nanosheettransistors, and nanowire transistors) where it may be desirable toprovide greater gate-to-source junction overlap and relatively lessgate-to-drain junction overlap. In embodiments wherein FinFET devicesare formed, the channels 50C are portions of monolithic semiconductorfins. For nanosheet or nanowire transistors, fins comprising thechannels may include stacked nanosheets or nanowires. In someembodiments, n-type MOSFETs and p-type MOSFETs formed on the samesubstrate may have the same or different channel materials. For example,an n-type FinFET may include a channel comprising a portion of a siliconfin and a p-type FinFET may have a silicon germanium fin channel.

There are numerous techniques used by those skilled in the art to removematerial at various stages of creating a semiconductor structure. Asused herein, these processes are referred to generically as “etching”.For example, etching includes techniques of wet etching, dry etching,chemical oxide removal (COR) etching, and reactive ion etching (RIE),which are all known techniques to remove select material when forming asemiconductor structure. The techniques and application of etching arewell understood by those skilled in the art and, as such, a moredetailed description of such processes is not presented herein.

Although the overall fabrication method and the structures formedthereby are novel, certain individual processing steps required toimplement the method may utilize conventional semiconductor fabricationtechniques and conventional semiconductor fabrication tooling. Thesetechniques and tooling will already be familiar to one having ordinaryskill in the relevant arts given the teachings herein. Moreover, one ormore of the processing steps and tooling used to fabricate semiconductordevices are also described in a number of readily availablepublications, including, for example: James D. Plummer et al., SiliconVLSI Technology: Fundamentals, Practice, and Modeling 1st Edition,Prentice Hall, 2001 and P. H. Holloway et al., Handbook of CompoundSemiconductors: Growth, Processing, Characterization, and Devices,Cambridge University Press, 2008, which are both hereby incorporated byreference herein. It is emphasized that while some individual processingsteps are set forth herein, those steps are merely illustrative, and oneskilled in the art may be familiar with several equally suitablealternatives that would be applicable.

It is to be appreciated that the various layers and/or regions shown inthe accompanying figures may not be drawn to scale. Furthermore, one ormore layers of a type commonly used in such integrated circuit devicesmay not be explicitly shown in a given figure for ease of explanation.This does not imply that the layer(s) not explicitly shown are omittedin the actual integrated circuit device.

Given the discussion thus far, it will be appreciated that, in generalterms, an exemplary asymmetric field-effect transistor device includes asemiconductor substrate 32 including a first region, a second region,and a channel region 50C between the first and second regions. The firstregion includes a recess 44′ extending vertically therein while thesecond region lacks a recess. A gate electrode 58 is operativelyassociated with the channel region 50C of the substrate. A gatedielectric layer 56 is between the gate electrode and the channelregion. A doped epitaxial source region 50A is on the first region ofthe semiconductor substrate and extends within the recess, as shown inFIGS. 10A and 10B. A doped epitaxial drain region 50B is on the secondregion of the semiconductor substrate. The semiconductor substrate 32may include a semiconductor fin 32′, the channel region and the recessbeing within the semiconductor fin and the drain region being on anunrecessed portion of the fin as schematically illustrated in FIGS. 10Band 10C. The source region 50A may extend beneath a portion of the gatedielectric layer 56, such as shown in FIG. 10A. The source region mayfurther extend beneath a portion of the gate electrode 58.

A method of fabricating asymmetric field-effect transistor devicesincludes obtaining a structure including a semiconductor substratehaving a plurality of parallel fins, the fins including first portionsincluding recesses, second portions lacking recesses, and channelregions between the first and second portions. FIG. 6 schematicallyillustrates an exemplary structure. Embedded source regions areepitaxially grown within the recesses in the first portions of the finsand cladded drain regions are epitaxially grown on the second,unrecessed portions of the fins. A gate dielectric layer 56 is depositedover the channel regions of the fins and metal gates 58 are formed onthe gate dielectric layer, as shown in FIG. 9. The fabrication methodmay further include forming a plurality of dummy gates 38 on thestructure, the dummy gates extending perpendicularly with respect to theplurality of parallel fins 32′. The recesses 44′ are formed in the firstportions of the substrate between pairs of the plurality of dummy gatesand include undercut portions extending beneath the dummy gates, asshown in FIG. 5. The dummy gates are ultimately replaced with the metalgates 58. The source regions and the drain regions are grownsimultaneously in some embodiments using the same precursor gases. Insome embodiments, the fabrication method further includes formingdielectric columns 54 between the dummy gates and extending verticallyover the source and drain regions, such as shown in FIG. 8. The dummygates are then removed to form trenches between the dielectric columns.Sidewall spacers 46 are formed on the sidewalls of the dielectriccolumns, possibly following trimming of the dielectric columns to reducethe widths thereof. One or more embodiments of the fabrication methodinclude forming sacrificial mandrels 36 on the semiconductor substrate,the dummy gates being formed as spacers on sidewalls of the sacrificialmandrels using a sidewall image transfer process. A structure as shownin FIG. 2 may accordingly be obtained. The sacrificial mandrels areremoved from the dummy gates to form a plurality of first verticaltrenches 44 as shown in FIG. 4. Dielectric columns 54 are formed withinthe plurality of first vertical trenches 44 subsequent to forming thesource regions. The fabrication method may further include forming asecond vertical trench 40 between a pair of the dummy gates 38 as shownin FIG. 2. The second vertical trench is filled with a filling material42 having a different composition from the mandrels and dummy gates,which can accordingly be etched selectively with respect to each other.The filling material 42 is removed selectively with respect to the dummygates to expose the second portions of the semiconductor substrate, asshown in FIG. 6. The second vertical trench is filled with one of thedielectric columns 54 subsequent to drain epitaxy.

At least a portion of the techniques described above may be implementedin an integrated circuit. In forming integrated circuits, identical diesare typically fabricated in a repeated pattern on a surface of asemiconductor wafer. Each die includes a device described herein, andmay include other structures and/or circuits. The individual dies arecut or diced from the wafer, then packaged as an integrated circuit. Oneskilled in the art would know how to dice wafers and package die toproduce integrated circuits. Any of the exemplary devices illustrated inthe accompanying figures, or portions thereof, may be part of anintegrated circuit. Integrated circuits so manufactured are consideredpart of this invention.

Those skilled in the art will appreciate that the exemplary structuresdiscussed above can be distributed in raw form (i.e., a single waferhaving multiple unpackaged chips), as bare dies, in packaged form, orincorporated as parts of intermediate products or end products thatbenefit from having asymmetric transistors therein formed in accordancewith one or more of the exemplary embodiments.

The illustrations of embodiments described herein are intended toprovide a general understanding of the various embodiments, and they arenot intended to serve as a complete description of all the elements andfeatures of apparatus and systems that might make use of the circuitsand techniques described herein. Many other embodiments will becomeapparent to those skilled in the art given the teachings herein; otherembodiments are utilized and derived therefrom, such that structural andlogical substitutions and changes can be made without departing from thescope of this invention. It should also be noted that, in somealternative implementations, some of the steps of the exemplary methodsmay occur out of the order noted in the figures. For example, two stepsshown in succession may, in fact, be executed substantiallyconcurrently, or certain steps may sometimes be executed in the reverseorder, depending upon the functionality involved. The drawings are alsomerely representational and are not drawn to scale. Accordingly, thespecification and drawings are to be regarded in an illustrative ratherthan a restrictive sense.

Embodiments are referred to herein, individually and/or collectively, bythe term “embodiment” merely for convenience and without intending tolimit the scope of this application to any single embodiment orinventive concept if more than one is, in fact, shown. Thus, althoughspecific embodiments have been illustrated and described herein, itshould be understood that an arrangement achieving the same purpose canbe substituted for the specific embodiment(s) shown; that is, thisinvention is intended to cover any and all adaptations or variations ofvarious embodiments. Combinations of the above embodiments, and otherembodiments not specifically described herein, will become apparent tothose of skill in the art given the teachings herein.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting. As used herein, thesingular forms “a,” “an” and “the” are intended to include the pluralforms as well, unless the context clearly indicates otherwise. It willbe further understood that the terms “comprises” and/or “comprising,”when used in this specification, specify the presence of statedfeatures, steps, operations, elements, and/or components, but do notpreclude the presence or addition of one or more other features, steps,operations, elements, components, and/or groups thereof. Terms such as“bottom”, “top”, “above”, “over”, “under” and “below” are used toindicate relative positioning of elements or structures to each other asopposed to relative elevation. If a layer of a structure is describedherein as “over” or adjoining another layer, it will be understood thatthere may or may not be intermediate elements or layers between the twospecified layers. If a layer is described as “directly on” anotherlayer, direct contact of the two layers is indicated.

The corresponding structures, materials, acts, and equivalents of meansor step-plus-function elements, if any, in the claims below are intendedto include any structure, material, or act for performing the functionin combination with other claimed elements as specifically claimed. Thedescription of the various embodiments has been presented for purposesof illustration and description, but is not intended to be exhaustive orlimited to the forms disclosed. Many modifications and variations willbe apparent to those of ordinary skill in the art without departing fromthe scope and spirit thereof. The embodiments were chosen and describedin order to best explain principles and practical applications, and toenable others of ordinary skill in the art to understand the variousembodiments with various modifications as are suited to the particularuse contemplated.

The abstract is provided to comply with 37 C.F.R. § 1.72(b), whichrequires an abstract that will allow the reader to quickly ascertain thenature of the technical invention. It is submitted with theunderstanding that it will not be used to interpret or limit the scopeor meaning of the claims. In addition, in the foregoing DetailedDescription, it can be seen that various features are grouped togetherin a single embodiment for the purpose of streamlining the invention.This method of invention is not to be interpreted as reflecting anintention that the claimed embodiments require more features than areexpressly recited in each claim. Rather, as the appended claims reflect,the claimed subject matter may lie in less than all features of a singleembodiment. Thus the following claims are hereby incorporated into theDetailed Description, with each claim standing on its own as separatelyclaimed subject matter.

Given the teachings provided herein, one of ordinary skill in the artwill be able to contemplate other implementations and applications ofthe techniques and disclosed embodiments. Although illustrativeembodiments have been described herein with reference to theaccompanying drawings, it is to be understood that illustrativeembodiments are not limited to those precise embodiments, and thatvarious other changes and modifications are made therein by one skilledin the art without departing from the scope of the appended claims.

1. An asymmetric field-effect transistor device comprising: asemiconductor substrate including a semiconductor fin comprising a firstregion, a second region, and a channel region within the semiconductorfin between the first and second regions, the first region including arecess extending vertically within the semiconductor fin, the secondregion comprising an unrecessed portion of the semiconductor fin; a gateelectrode including a drain side and a source side, the gate electrodebeing operatively associated with the channel region; a gate dielectriclayer between the gate electrode and the channel region; a doped,embedded epitaxial source region on the first region of thesemiconductor substrate and extending within the recess; and a doped,cladded epitaxial drain region on the second region of the semiconductorsubstrate.
 2. (canceled)
 3. The asymmetric field-effect transistordevice of claim 1, wherein the source region extends beneath a portionof the gate dielectric layer and laterally further towards the channelregion than the drain region.
 4. The asymmetric field-effect transistordevice of claim 3, wherein the source region, but not the drain region,extends beneath a portion of the gate electrode.
 5. The asymmetricfield-effect transistor device of claim 3, further including: a sourcecontact electrically connected to the source region; a drain contactelectrically connected to the drain region, and a plurality of verticalsidewall spacers, each source contact and each drain contact beingpositioned between a pair of the plurality of vertical sidewall spacers.6. The asymmetric field-effect transistor device of claim 5, wherein thesource region includes top surfaces adjoining one of the pairs of theplurality of vertical sidewall spacers.
 7. The asymmetric field-effecttransistor device of claim 6, wherein the drain region includes topsurfaces adjoining one of the pairs of the plurality of verticalsidewall spacers.
 8. The asymmetric field-effect transistor device ofclaim 1, further including: a source contact electrically connected tothe source region; a drain contact electrically connected to the drainregion, and a plurality of vertical sidewall spacers, each sourcecontact and each drain contact being positioned between a pair of theplurality of vertical sidewall spacers.
 9. The asymmetric field-effecttransistor device of claim 8, wherein the source region and the drainregion both include lateral portions extending beneath one of the pairsof the plurality of the vertical sidewall spacers.
 10. The asymmetricfield-effect transistor device of claim 1, wherein the recess extendsbetween twenty and sixty nanometers within the semiconductor fin. 11.The asymmetric field-effect transistor device of claim 1, wherein thesemiconductor substrate includes a plurality of parallel semiconductorfins, further including an electrically insulating, shallow trenchisolation layer having a top surface between the plurality of parallelsemiconductor fins, the doped epitaxial source region, but not the dopedepitaxial drain region, extending beneath the top surface of the shallowtrench isolation layer.
 12. An asymmetric field-effect transistorstructure comprising: a plurality of parallel semiconductor fins, eachof the semiconductor fins including sidewalls and a channel region; agate electrode extending across the semiconductor fins, the gateelectrode having a first side and a second side and being operativelyassociated with the channel regions of the semiconductor fins; a gatedielectric layer between the gate electrode and each of the channelregions; an electrically insulating, shallow trench isolation layerhaving a top surface, the semiconductor fins having bottom portionsembedded within the shallow trench isolation layer; a recess extendingwithin each of the semiconductor fins on the first side of the gateelectrode, the semiconductor fins including unrecessed portions on thesecond side of the gate electrode; a plurality of embedded, epitaxialsource regions on the semiconductor fins, each of the epitaxial sourceregions being doped and extending within one of the recesses and beneaththe top surface of the shallow trench isolation layer; and a pluralityof cladded, doped epitaxial drain regions on the sidewalls of theunrecessed portions of the semiconductor fins, none of the dopedepitaxial drain regions extending beneath the top surface of the shallowtrench isolation layer.
 13. The asymmetric field-effect transistorstructure of claim 12, wherein the doped epitaxial source regions havegreater volumes than the doped epitaxial drain regions.
 14. Theasymmetric field-effect transistor structure of claim 13, wherein thedoped epitaxial source regions extend beneath portions of the gatedielectric layer.
 15. The asymmetric field-effect transistor structureof claim 14, wherein the doped epitaxial source regions extend beneathportions of the gate electrode.
 16. The asymmetric field-effecttransistor structure of claim 14, further including: source contactselectrically connected to the doped epitaxial source regions; draincontacts electrically connected to the doped epitaxial drain regions,and a plurality of vertical sidewall spacers, each source contact andeach drain contact being positioned between a pair of the plurality ofvertical sidewall spacers.
 17. The asymmetric field-effect transistorstructure of claim 16, wherein the doped epitaxial source regionsinclude top surfaces adjoining pairs of the plurality of verticalsidewall spacers.
 18. The asymmetric field-effect transistor structureof claim 16, wherein the recesses have depths between twenty and sixtynanometers. 19-20. (canceled)
 21. The asymmetric field-effect transistordevice of claim 1, further including doped junctions extendinglaterally, respectively, from the source region and the drain region,there being a greater overlap between the doped junction extending fromthe source region and the gate electrode than between the doped junctionextending from the drain region and the gate electrode.
 22. Theasymmetric field-effect transistor device of claim 21, wherein thesource region has a greater volume than the drain region.